The present invention relates to a semiconductor device pattern evaluating system for, in a semiconductor manufacturing process, evaluating whether the result of processing of each circuit pattern formed on a wafer is good or bad, and a method therefor, and particularly to a technology effective if applied to a method for estimating the property of a device circuit formed by a semiconductor device pattern to thereby evaluate the semiconductor device pattern.
In a conventional semiconductor circuit pattern relatively long in gate length, an electric property of a transistor has principally depended on a wiring width (gate length) of a gate wiring portion. Therefore, a scanning electron microscope (critical-dimension SEM) dedicated to measurement has heretofore been used to measure and manage the wiring width of the pattern in a semiconductor manufacturing process.
With shrink rapidly advanced in recent years, however, short channeling of each transistor has been put forward, and shape parameters for determining a device property have become more than just the wiring width.
The difference in pattern cross-sectional shape of a gate wiring will now be explained.
FIG. 2 is a diagram for describing the shape of a gate wiring pattern and abnormal shapes of gate wiring patterns.
Referring to FIG. 2, FIG. 2A shows a shape considered to be most desirable in general. A sidewall angle of each pattern sidewall is substantially vertical, and no bottom corner roundness or the like occurs in a pattern bottom.
On the other hand, FIG. 2B shows the shape of a taper, FIG. 2C illustrates the shape of a retrograde, and FIG. 2D depicts the shape of a footing (bottom corner roundness). These shapes are indicative of shape abnormalities caused because a condition for a manufacturing process is not suitable.
Since a gate length assumes the size of the pattern bottom, it is of importance that the size of the bottom is measured regardless of the shape.
In a gate process, ion implantation is performed with the wiring pattern as a mask to form a source/drain of the transistor. Therefore, the inclination of each pattern sidewall and the bottom corner roundness state exert an influence on the result of processing in the ion-implantation process, so that a device property varies.
While the evaluation of a pattern's three-dimensional shape is very important in this way, the conventional critical-dimension SEM has encountered difficulties in evaluating such a three-dimensional shape by only dimensions of a two-dimensional shape, like the width of a wiring pattern, the diameter of a contact hole, etc. Since a change in pattern shape makes a cause and hence the result of a subsequent process such as ion implantation is affected by its cause, there is a lot of uncertainty about the relationship between variations in three-dimensional shape and the property of a device formed as a result thereof.
In the scale-down advanced product as described above, it is becoming difficult to allow only the conventional wiring size to compensate for the device property. In order to ensure a desired device property in contrast, there is a need to clarify to which portion of a pattern's three-dimensional shape attention is made and with what degree of accuracy it should be managed.
However, the conventional critical-dimension SEM (Scanning Electron Microscope) is accompanied by problems that it is difficult to acquire information about the three-dimensional pattern shape, and as a device structure and a process become complex, it becomes also difficult to estimate which shape of the resultant three-dimensional pattern shape information is effective for any type of property.
If the relationship of these can be made clear, then the standard for process control becomes definite and hence stable production is enabled.
Incidentally, there is known one described in Japanese Patent Laid-open No. Hei 7(1995)-27549 as a related art relevant to the measurement of each pattern by using a critical-dimension SEM.